AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Sep 24, 2026 - SystemVerilog
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axi
Here are 192 public repositories matching this topic...
Code generation tool for control and status registers
asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb systemrdl register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents
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Sep 11, 2026 - Ruby
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface
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Aug 10, 2026 - Verilog
A Fast, Low-Overhead On-chip Network
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Oct 2, 2026 - SystemVerilog
Control and status register code generator toolchain
asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model
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Sep 1, 2026 - Python
Network on Chip Implementation written in SytemVerilog
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Aug 27, 2022 - SystemVerilog
Simple single-port AXI memory interface
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Jun 7, 2024 - SystemVerilog
OPAE porting to Xilinx FPGA devices.
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Aug 5, 2020 - Coq
RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.
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Mar 13, 2025 - Verilog
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
simulation vhdl verilog questasim ghdl avalon memory-model test-bench pli verilog-components verilator axi nvc dpi-c cosimulation vivado-simulator verilog-testbenches
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Feb 2, 2026 - VHDL
This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects
protocol verification eda rtl verilog systemverilog alu vlsi modelsim uvm verilog-hdl axi apb ahb verilog-project vlsi-design design-verification vlsi-project axi-lite system-verilog-testbench
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May 23, 2026 - SystemVerilog
Agent-ergonomic CLI for TypeSafe's Jev: fast calibrated judgments (pick, rate, check, rank, triage, guard) from the shell
cli developer-tools typesafe codex ai-agents axi prompt-injection llm-guardrails claude-code agent-safety claude-code-hooks jev
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Oct 1, 2026 - TypeScript
数字IC验证学习笔记：SV/UVM/AMBA总线（AXI/APB/AHB/AXI-Lite/AXI-Stream）+ 数字IC验证校招面经
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Sep 14, 2026
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