ai-hardware

Master AI inference, AI agent harness systems, and hardware engineering — then design a physical AI chip. That is the goal.

PMSG is face computer / wearable platform using Seeed Studio XIAO, This where you can find code to flash you device

🦞 ClawBox — Your private AI assistant on NVIDIA Jetson. Setup wizard, dashboard, and 580+ skills. Plug in, scan QR, done.

Evidence profiles for AI-generated RTL that expose what functional benchmarks miss. Seeking collaborators, design partners, and validation

A Go CLI tool to benchmark local LLMs via Ollama, measuring Time To First Token (TTFT) and throughput on your specific hardware.

AI accelerators, edge inference devices, compilers, runtimes, benchmarks, and research for building and evaluating machine-learning systems.

A curated list of open-source AI hardware, IoT, wearables, robotics, and edge AI projects.

Garuda: CVXIF coprocessor optimizing batch-1 attention microkernels with 7.5-9× lower p99 latency. RISC-V INT8 MAC accelerator for transformer inference.

Make your own talking skull for halloween in 2 hours.

This is the official Arduino library for N2CMU (Neural Network Coprocessing Microcontroller Unit) available on Arduino Package Manager and PlatformIO.

大模型久困云端，故押注百年未来于“AI硬件+端云协同”，期待着AGI与真实幻境的完美重叠。也是祈光的原意之一：祈光同行。 We Are Praying for Light.

T1C — Open-source AI accelerator architecture by ADDX Entp, created by Sarthak. Explore open silicon, digital in-memory computing, and LLM hardware.

Tool, Toy, or Trash? An agent skill that audits any AI gadget from its product page: brand-blinded, three independent auditors, one safety veto.

Feedforward Neural Network Coprocessing Microcontroller Unit (CPC via UART) for STM32F103C8T6 Bluepill Development Board written purely in TinyGo.

SystemVerilog implementations of fundamental neural network structures, designed for synthesis on FPGAs.

Installable agent skill for safely configuring FoloToy character personas, opening lines, and voices

A synthesizable 32-bit RISC-V RV32I single-cycle processor integrated with a memory-mapped MAC AI accelerator for hardware vector dot-product offloading, built in SystemVerilog with full verification and Python software toolchain.

Open hardware desktop AI node: 4× Tesla V100, 128GB HBM2, PCIe/NVLink topology and V-Core liquid/air cooling.

End-to-end ASIC SoC design and functional verification of a lightweight machine learning accelerator using SystemVerilog and UVM. Includes Python automation for test generation and result analysis. Built to simulate real-world ML silicon validation at scale.

Hardware-level AI Matrix Multiplication Accelerator (Systolic Array) in SystemVerilog using AXI4-Stream, verified via Python & Cocotb co-simulation.