Skip to content
View Rohankumar2201's full-sized avatar
🎯
Focusing
🎯
Focusing
5 followers · 3 following

Achievements

Achievement: YOLOAchievement: Quickdraw

Achievements

Achievement: YOLOAchievement: Quickdraw

Block or report Rohankumar2201

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Rohankumar2201/README.md

⚡ About Me

I'm an Electronics & Communication Engineering student building real hardware-adjacent systems instead of just studying them — RTL cores, FPGA-targeted designs, and autonomous embedded systems.

  • 🔭 Currently building a parameterized UART controller in SystemVerilog — FIFO, oversampled TX/RX FSMs, CDC synchronization, self-checking testbench
  • 🧠 Built a full 5-stage pipelined RV32I RISC-V core in Verilog, simulated with Icarus Verilog + GTKWave
  • 🌱 Currently deep in digital design verification, CDC, and FPGA implementation flows

🛠️ Tech Stack

HDL / Digital Design: SystemVerilog · Verilog · RTL Design · FSM Design · CDC Handling Tools: Icarus Verilog · GTKWave · Xilinx Vivado · ModelSim Embedded: ESP32 · ATmega328P · nRF24L01+ · FreeRTOS Architecture: RISC-V (RV32I) · Pipelining · Hazard Detection

📊 GitHub Stats

🌐 Connect

Pinned Loading

  1. 4bit-cpu-verilog 4bit-cpu-verilog Public

    Verilog

  2. Sankshepa-kmap-solver Sankshepa-kmap-solver Public

    Client-side Karnaugh map minimizer (2–4 variables) using Quine-McCluskey. Outputs both minimized SOP and POS expressions with color-coded implicant groups.

    JavaScript

  3. verilog-templates verilog-templates Public

    48 reusable Verilog & SystemVerilog RTL templates for digital design, verification and FPGA development. Searchable library with copy-ready code.

    TypeScript